//`include "uvm_pkg.sv"
//`include "uvm_macros.svh"
`include "ahb_if.sv"

`define EZCHIP_DUT_AHB_LITE_MST_VIF(HIER, VIF) \
    force HIER``.HADDR = ``VIF``.HADDR;\
    force HIER``.HBURST = ``VIF``.HBURST;\
    force HIER``.HSIZE = ``VIF``.HSIZE;\
    force HIER``.HTRANS = ``VIF``.HTRANS;\
    force HIER``.HWDATA = ``VIF``.HWDATA;\
    force HIER``.HWRITE = ``VIF``.HWRITE;\
    force VIF``.HRDATA = ``HIER``.HRDATA;\
    force VIF``.HRESP = ``HIER``.HRESP;\
    force VIF``.HRESETn = rst_n;\
    force VIF``.HREADYOUT = 1'b1;\
    force VIF``.HREADY = 1'b1;
    //force VIF``.HREADYOUT = 1'b1;
    //force VIF``.HRESETn == ``HIER``HRESETn;\
    //force VIF``.HREADY = ``HIRE``.HREADY;
    //force HIER``.HSELx = ``VIF``.HSELx;\ 
    //force HIER``.HRESETn = ``VIF``.HRESETn;\ 
    

module TestbenchTop(/*AUTOARG*/);
    
  import uvm_pkg::*;
  import ezchip_tests_pkg::*;
  wire tb_clk        ;
  reg rst_n;
  reg  tb_clk50M      ;
  reg  tb_clk100M     ;
  reg  tb_clk150M     ;
  reg  tb_clk200M     ;
  AHB_IF u_ahb_vif0(tb_clk);
  //AHB_IF u_ahb_vif0(u_top.u6_mcu.u0_cm0pmtbintegration.HCLK);

  parameter CLK_PERIOD50M   = 50  ;
  parameter CLK_PERIOD100M  = 100 ;
  parameter CLK_PERIOD150M  = 150 ;
  parameter CLK_PERIOD200M  = 200 ;


  
  initial begin
  `EZCHIP_DUT_AHB_LITE_MST_VIF(u_top.u6_mcu.u0_cm0pmtbintegration, u_ahb_vif0)
    uvm_config_db#(virtual AHB_IF)::set(uvm_root::get(), "*", "regAHB_vif", u_ahb_vif0);
    run_test();
  end
  


  initial begin 
    #1ns; 
    tb_clk50M  = 1'b1  ;
    tb_clk100M = 1'b1  ;
    tb_clk150M = 1'b1  ;
    tb_clk200M = 1'b1  ;
  end

  always 
     #(CLK_PERIOD50M/2.0)         tb_clk50M = ~tb_clk50M      ;

  always 
     #(CLK_PERIOD100M/2.0)        tb_clk100M = ~tb_clk100M    ;

  always 
     #(CLK_PERIOD150M/2.0)        tb_clk150M = ~tb_clk150M    ;

  always 
    #(CLK_PERIOD200M/2.0)        tb_clk200M = ~tb_clk200M    ;


    //Generate Clock


  `ifdef CLK50M
     assign tb_clk = tb_clk50M     ;
  `elsif CLK100M
     assign tb_clk = tb_clk100M    ;
  `elsif CLK150M
     assign tb_clk = tb_clk150M    ;
  `else
     assign tb_clk = tb_clk200M    ;
  `endif

  initial begin

     #500ms ;
     $display("Warning : simulation has already run for 500ms, Call finish!");
     $finish ;
  
  end //for 

 /*top AUTO_TEMPLATE ( 
                                 .\(.*\)    (),     
                                );*/

 top u_top(/*AUTOINST*/);

 initial begin
   rst_n = 1'b0;
   repeat(10) @(posedge tb_clk);
   rst_n = 1'b1;
 end


 initial begin
   #500ms ;
   $display("Warning : simulation has already run for 500ms, Call finish!"); 

   $finish;
 end 

endmodule : TestbenchTop 
//Local Variables:
//verilog-library-directories:("./" "$AQARCH/chip/mc/src/v4" "$AQARCH/chip/mc/src/decoder")
//verilog-library-extensions:(".v" ".vh")
//End:

